In a known embodiment, semiconductor memory cells with random access to information stored in a storage capacitor include, as dynamic memory cells, a planar select transistor and a deep trench in which the storage capacitor is formed. At the planar select transistor, a gate contact is arranged on the substrate surface and is formed directly between two doped diffusion regions at the substrate surface. In this document, the term “gate contacts” is used to refer to all active surfaces of the transistor, i.e., the interfaces of word lines and active areas, which, for example, may be separated from one another only by a very thin gate oxide layer.
A bit line contact, via which an electric charge released by the select transistor can be read from the storage capacitor, is connected to a first of the diffusion regions. The other diffusion region is connected via a buried strap to a conductive material, typically polysilicon, in the trench arranged next to the diffusion region. The conductive material in the deep trench functions as a storage electrode for the capacitor, while, for example, a deeply buried doped plate in the substrate serves as a second capacitor electrode, with a thin dielectric layer located between the two electrodes. A word line controls the select transistor via the gate contact for switching an electrically conductive connection from the storage capacitor to the bit line.
To achieve the highest possible integration densities in a memory cell array, it is generally endeavored to minimize the surface area taken up by an individual semiconductor memory cell. For a memory cell with a planar select transistor, the footprint of the smallest memory cell, which can be fabricated conventionally is 8 F2, where F is the smallest length dimension that it is possible to produce by lithography (minimum feature size) on a wafer. In production installations for memory products, F is currently undergoing a transition from 0.15 μm to 0.13 μm.
The area of 8 F2 results from the sum of the two structures produced by lithography—namely the gate contact and the trench—in a semiconductor memory cell, which for a planar arrangement of the select transistor must be at a distance of approximately 1 F from one another, and the required trench isolation, which isolates the active diffusion areas of the cell from those of an adjacent memory cell.
Semiconductor memory cells according to the prior art with trench and planar select transistor are known, for example, from documents EP 0 908 948 A2 and EP 0 949 684 A2.
FIG. 1 illustrates an example of a layout, which is currently in widespread use for a semiconductor memory cell, with an adjacent cell additionally being included in the figure in order to illustrate their relative arrangement in a memory cell array. The two semiconductor memory cells 1, 2 are arranged mirror-symmetrically about an interface 30, which is perpendicular to the plane of the drawing in FIG. 1. The interface 30 and also the interfaces between the other sides of the memory cells represent their imaginary, logic outer limits and serve to facilitate the assignment of individual structures in a dense, periodic array to the respective memory cells. In the present example, the interface 30 is defined by a mirror plane of the structures assigned to two adjacent memory cells.
In the diagrammatic plan view shown in FIG. 1, the trenches 12, 13 are illustrated in the form of rectangles, as they are formed on a mask for patterning the trenches on the wafer. However, the projected image on the wafer depicts trenches with oval cross-sections 22 and 23, respectively. A gate contact 10, which is connected to a word line WL and forms a transistor, allows electrically conductive connection of the trench 12, via a first diffusion region 14, to a second diffusion region 16, with which contact is made from above, in the plane of the drawing shown in FIG. 1, by a bit line contact 18. The memory cells 1 and 2 share the bit line contact 18 and the second diffusion region 16 and 17. The bit line contact 18 is connected to a bit line BL running in the X direction above the plane of the drawing shown in FIG. 1.
The definition of the diffusion regions 14, 15, 16, 17 in the two cells 1, 2 and of the isolation trench 20 for isolating the active areas of the semiconductor memory cells 1, 2 from further, adjacent semiconductor memory cells (not shown) is achieved by the lithographic projection of precisely one structure 31 into, in each case, two cells in the memory cell array to be formed on the wafer. The bar-like structure 31 is initially formed as a resist mask on the surface so that the shallow isolation trenches 20 (shallow trench isolation, STI) can be formed in the silicon substrate in an etching step. After the resist mask has been removed, an oxide is deposited in the trenches, for example in an HDP process (High-Density Plasma process), and then planarized. Then, the gate contacts 10, 11, the word lines WL and, by implantation with subsequent activation of the diffusion regions 14-17, are formed.
In a conventional method for forming the memory cells 1, 2, first of all the trench is formed in a substrate. A dielectric layer which serves as capacitor dielectric is deposited on the inner wall of the trench. The trench is then filled for the first time with a conductive material. The conductive material, together with the dielectric layer, is etched back, so that the capacitor electrode is formed only in a lower region of the trench. Above the etched-back conductive material which comprises, for example, a polysilicon, an insulation collar consisting of oxide is formed at the trench inner wall in a CVD process. Then, in a second filling process, conductive material is deposited into the trench for a second time using a CVD process and etched back, so that there is a distance of, for example, 100 nm from the top edge of the conductive material to the silicon surface. The insulation collar, which projects above this top edge, is removed in an etching step, so that the trench inner wall, which consists of silicon, is uncovered in an upper region of the trench. Then, a third filling with conductive material, which is now highly doped for outdiffusion under the influence of heat, is deposited.
In the completed memory cell, passive second word lines WLs, which can be used to drive gate contacts of adjacent memory cells (not shown in FIG. 1), run over the trenches 12, 13. Therefore, an insulation layer for the second, passive word line WL running above is required above the conductive material of the third filling in the trenches 12, 13. This is made possible by deposition of an oxide above the conductive material of the third filling in a joint step with the filling of the shallow trench isolation 20.
The shallow trench isolation extends sufficiently deep into the substrate for it to reach the top edge of the insulation collar at the trench inner wall, so that there is no electrically conductive connection produced between the adjacent trenches 22, 23 of two adjacent memory cells. In this context, it should be borne in mind that the shallow isolation trench 20 covers approximately half the diameter of the trench 12, so that a sufficiently large buried strap of the conductive material is still available, for example, in the upper region of the trench 12 to the substrate of the diffusion region 14.
On the other hand, if the structure 31 is positioned inaccurately on the trench structure 12, on the one hand the contact surface at the buried strap may be reduced in size or even prevented altogether if an excessively small overlap region 33 is formed between the structure 31 and the trench structure 12. On the other hand, however, if an excessively large overlap region 33 is formed, an undesired diffusion contact may occur on the opposite side of the trench 12. Consequently, to maintain the quality of semiconductor memory cells according to the prior art of this nature, very high demands are imposed on the positional accuracy and sizes of structures and/or very tight tolerances 32 are required with regard to positional accuracy or critical dimension (CD). However, these demands are becoming increasingly difficult to satisfy using lithographic techniques with the constant decrease in feature size.